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1 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x single-chip 8-bit microcontroller advanced information feature ? high performance cmos rom cpu ? low voltage operation (2.7v~5.5v) ? up to 40mhz operation (3.5mhz to 40mhz) ? three 16-bit timer/counters ? 256 bytes of on-chip data ram ? 64 kbytes on-chip program memory ? 32 programmable i/o lines ? on-chip watch-dog-timer (wdt) ? 6 interrupt sources ? rom code protection ? two priority levels ? power saving idle and power down modes ? 64 k external program memory space ? 64 k external data memory space ? available in plcc, pqfp, and pdip package ? four 8-bit i/o ports ? full-duplex enhanced uart compatible with the stan- dard 80c51 and the 80c52 ? extended temperature range (-40c to +85 c) general description the single-chip 8-bit microcontroller is manufactured in mxic's advanced cmos process. this device uses the same powerful instruction set, has the same architec- ture, and is pin-to-pin compatible with the existing 80c51. the added features make it an even more powerful microcontroller for applications that require clock out- put, and up/down counting capabilities such as motor control. it also has a more versatile serial channel that facilitates multi-processor communications. pin configurations 40 pdip 44 plcc 44 pqfp mx10l8050x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (t2) p1.0 (t2ex) p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 reset (rxd) p3.0 (txd)p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 (wr) p3.6 (rd) p3.7 xtal2 xtal1 vss 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea ale psen p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8) mx10l8050x p1.5 p1.6 p1.7 rst p3.0 n.c. p3.1 p3.2 p3.3 p3.4 p3.5 p0.4 p0.5 p0.6 p0.7 ea n.c. ale psen p2.7 p2.6 p2.5 p1.4 p1.3 p1.2 p1.1 p1.0 n.c. vcc p0.0 p0.1 p0.2 p0.3 p3.6 p3.7 xtal2 xtal1 vss n.c. p2.0 p2.1 p2.2 p2.3 p2.4 64440 39 34 29 7 12 17 18 23 28 1 1 11 12 22 23 33 34 44 p0.4 p0.5 p0.6 p0.7 ea n.c. ale psen p2.7 p2.6 p2.5 p1.5 p1.6 p1.7 rst p3.0 n.c. p3.1 p3.2 p3.3 p3.4 p3.5 p1.4 p1.3 p1.2 p1.1 p1.0 n.c. vcc p0.0 p0.1 p0.2 p0.3 p3.6 p3.7 xtal2 xtal1 vss n.c. p2.0 p2.1 p2.2 p2.3 p2.4 mx10l8050x
2 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x block diagram port 0 drivers port 0 latch acc psw tmp2 port 1 latch port 1 drivers p1.0-p1.7 xtal2 xtal1 osc. tmp1 alu b register timing and control ram vcc vss ram addr. register instruction register port 2 latch stack pointer rom port 2 drivers buffer dptr program addr. register t0/t1/t2 sfrs timers port 3 latch port 3 drivers t3 watchdog timer pc incrementer program counter p0.0-p0.7 p2.0-p2.7 p3.0-p3.7 psen ale ea rst
3 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x pin descriptions vcc : supply voltage. vss : circuit ground. port 0 : port 0 is an 8-bit, open drain, bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pullups when emitting 1's, and can source and sink serveral ls ttl inputs. port 1 : port 1 is an 8-bit bidirectional i/o port with inter- nal pullups. the port 1 output buffers can drive ls ttl inputs. port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 1 pins that are exter- nally pulled low will source current (iil, on the data sheet) because of the internal pullups. in additional, port 1 serves the functions of the following special features of the mx10l8050x : port pin alternate function p1.0 t2 (exter nal count input to timer/ counter 2), clock-out p1.1 t2ex (timer/counter 2 capture/reload trigger and direction control) port 2 : port 2 is an 8-bit bidirectional i/o port with inter- nal pullups. the port 2 output buffers can drive ls ttl inputs. port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 2 pins that are exter- nally pulled low will source current (iil, on the data sheet) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pullups when emitting 1's. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 emits the contents of the p2 special function register. port 3 : port 3 is an 8-bit bidirectional i/o port with inter- nal pullups. the port 3 output buffers can drive ls ttl inputs. port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 3 pins that are exter- nally pulled low will source current (iil, on the data sheet) because of the internal pullups. port 3 also serves the function of various special fea- tures of the 8051 family, as listed below : port pin alternate function p3.0 rxd (serial input port) p3.1 txd (serial output port) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer 0 external input) p3.5 t1 (timer 1 external input) p3.6 wr (external data memory write sttobe) p3.7 rd (external data memory read strobe) process information this device is manufactured on a mxic cmos process. packages mx10l8050 0 p c temperature c=0 c to 070 c i=-40 c+085 c package p=pdip q=plcc f=pqfp rom size 0=64k bytes
4 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x rst : reset input. a high on this pin for two machine cycles while the oscillator is running resets the device. the port pins will be driven to their reset condition when a minimum vihi voltage is applied whether the oscilla- tor is running or not. an internal pulldown resistor per- mits a power-on reset with only a capacitor connected to vcc. ale : address latch enable output pulse for latching the low byte of the address during accesses to external memory. in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for exter- nal timing or clocking purposes. note, however, that one ale pulse is skipped during each access to exter- nal data memory. if desired, ale operation can be disabled by setting bit 5 of sfr location 87h (pcon). with this bit set, the pin is weakly pulled high. however, the ale disable feature will be suspended during a movx or movc instruction, idle mode, power down mode. the ale disable feature will be terminated by reset. when the ale disable fea- ture is suspended or terminated, the ale pin will no longer be pulled up weakly. setting the ale-disable bit has no affect if the micrcontroller is in external execu- tion mode. throughout the remainder of this data sheet, ale will refer to the signal coming out of the ale pin, and the pin will be referred to as the ale pin. psen : program store enable is the read strobe to ex- ternal program memory. when the mx10l8050x is executing code from external program memory, psen is activated twice each ma- chine cycle, except that two psen activations are skipped during each access to external data memory. ea/vpp : extrernal access enable. ea must be strapped to vss in order to enable the twiceto fetch code from external program memory locations 0000h to 0ffffh. ea will be internally latched on reset. ea should be strapped to vcc for internal program ex- ecutions. xtal1 : input to the inverting oscillator amplifier. xtal2 : output from the inverting oscillator amplifier. to drive the device from an external clock source, xtal1 should be driven, while xtal2 floats, as shown in fig- ure 4. there are no requirememts on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. an external oscillator may encounter as much as a 100 pf load at xtal1 when it starts up. this is due to inter- action between the amplifer and its feedback capaci- tance. once the external signal meets the vil and vih specifications the capacitance will not exceed 20 pf. c2 xtal2 xtal1 vss figure 3. oscillator connections c1, c2 = 30 pf is equal to or less than 10 pf for crystal for ceramic resonators,contact resonator manufacture. c1 n/c xtal1 vss xtal2 external oscillator signal figure 4. external clock drive configuration oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 3. either a quartz crystal or ceramic resonator may be used.
5 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x table 2. status of the external pins during idle and power down mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 data data data data idle external 1 1 float data address data power down internal 0 0 data data data data power down external 0 0 float data data data power down mode to save even more power, a power down mode can be invoked by software. if this mode, the oscillator is stopped and the instruction that invoked power down is the last instruction executed. the on-chip ram and special function registers retain their values until the power down mode is terminated. on the mx10l8050x either a hardware reset or an exter- nal interrupt can cause an exit from power down. re- set redefines all the sfrs but does not change the on- chip ram. an external interrupt allows both the sfrs and on-chip ram to retain their values. absolute maximum rating* ambient temperature under bias -40 c to +85 c storage temperature -65 c to +150 c voltage on any other pin to vss -0.5v to +6.5v iol per i/o pin 15ma power dissipation 1.5w (based on package heat transfer limitations, not de- vice consumption) idle mode the user's software can invoke the idle mode. when the microcontroller is in this mode, power consumption is reduced. the special function registers and the onboard ram retain their values during idle, but the pro- cessor stops executing instructions. idle mode will be exited if the chip is reset or if an enabled interrupt oc- curs. operating conditions symbol description min max units ta ambient temperature under bias commerical 0 +70 c industrial -40 +85 c vcc 2.7 5.5 v fosc oscillator frequency 3.5 40 mhz to properly terminate power down, the reset or external interrupt should not be executed before vcc is restored to its normal operating level, and must be held active long enough for the oscillator to restart and stabilize (nor- mally less than 10 ms). with an external interrupt, int0 and int1 must be en- abled and configured as level-sensitive. holding the pin low restarts the oscillator but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put the device into power down.
6 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x dc characteristics (over operating conditions) all parameter values apply to all devices unless otherwise indicated. symbol parameter min typ max unit test conditions (note 4) vil input low voltage -0.5 0.2 vcc-0.1 v vil1 input low voltage ea 0 0.2 vcc-0.3 v vih input high voltage 0.2 vcc+0.9 vcc+0.5 v (except xtal1, rst) vih1 input high voltage 0.7 vcc vcc+0.5 v (xtal1, rst) vol output low voltage (note 5) (ports 1, 2, and 3) 0.4 v iol=1.6 ma (note 1) vol1 output low voltage (note 5) (port 0, ale, psen) 0.4 v iol=3.2 ma (note 1) voh output high voltage 0.9 vdd v ioh=-10 ua (port 1, 2 and 3, ale, psen) 0.75 vdd v ioh=-30 ua 0.5 vdd v ioh=-60ua voh1 output high voltage 0.9 vdd v ioh=-80 ua (port 0 in external bus mode) 0.75 vdd v ioh=-300 ua 0.5 vdd v ioh=-800 ua iil logical 0 input current -50 ua vin=0.4v (ports 1, 2 and 3) ili input leakage current (port 0) 10 ua vin=vil or vih itl logical 1 to 0 transition current -750 ua vin=2v (ports 1, 2 and 3) industrial prst rst pulldown resistor 15 150 k ohm cio pin capacitance 10 pf @1 mhz, 25 c icc power supply current: (note 3) active mode at 40 mhz 60 ma idle mode at 40 mhz(70 c 5.5v) 28 ma power down mode 2 10 ua notes: 1. capacitive loading on ports 0 and 2 may cause noise pulses above 0.4v to be superimposed on the vols of ale and ports 1, 2 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. in ap plications where capacitive loading exceeds 100 pf, the noise pulses on these signlas may exceed 0.8v. it may be desirable to qualify ale or other signals with a schmitt triggers, or cmos-level input logic. 2. capacitive loading on ports 0 and 2 cause the voh on ale and psen to drop below the 0.9 vcc specification when the address l ines are stabilizing. 3. minimum vcc for power down is 2v. 4. typicals are based on a limited number of samples and are not guaranteed. the values listed are room temperature and 5v. 5. under steady state (non-transient) conditions, iol must be externally limited as follows: maximum iol per port pin: 10ma maximum iol per 8-bit port: port 0: 26ma ports 1, 2 and 3: 15ma maximum total iol for all output pins: 71ma if iol exceeds the test condition, vol may exceed the related specification. pins are not guaranteed to sink current greater t han the listed test conditions.
7 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0.0 4.0 8.0 12.0 16.0 20.0 freq at xtal1 (mhz) icc (ma) 24.0 28.0 36.0 max active mode typ active mode max idle mode max idle mode 32.0 note: icc max at 33 mhz is at 5v is + 10% vcc, while icc max at 24 mhz and below is at 5v + 20% vcc figure 5. 80c52/54/58 icc vs frequwncy mx10l8050x rst (nc) clock signal xtal2 xtal1 vss vcc vcc vcc icc vcc figure 6. icc test condition, active mode all other pins disconnected tclch = tchcl = 5ns p0 ea mx10l8050x rst (nc) clock signal xtal2 xtal1 vss vcc vcc vcc icc figure 7. icc test condition idle mode all other pins disconnected tclch = tchcl = 5ns p0 ea
8 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x explanation of the ac symbols each timing symbol has 5 characters. the first charac- ter is always a "t" (stands for time). the other charac- ters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a: address c: clock d: input data h: logic level high l: logic level low, or ale p: psen q: output data r: rd signal t: time v: valid w: wr signal x: no longer a valid logic level z: float for example, tavll = time from address valid to ale low tllpl = time from ale low to psen low 0.45v 0.2 vcc-0.1 tchcl tclcx tclcl tclch tchcx vcc-0.5 0.7 vcc figure 9. clock signal waveform for icc tests in active and idle modes. tclch = tchcl = 5 ns mx10l8050x rst (nc) xtal2 xtal1 vss vcc vcc vcc icc figure 8. icc test condition, power down mode vcc=2.0v to 6.0v all other pins disconnected p0 ea
9 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x ac characteristics (over operating conditions, load capacitance for port 0, ale/prog and psen = 100 pf, load capacitance for all other outputs = 80 pf) tck min. = 1/f max. (maximum operating frequency); tck=clock period symbol parameter 33 mhz unit min max external program memory tlhll ale pulse duration 20 - ns tavll address set-up time to ale 17 - ns tllax address hold time after ale 10 - ns tlliv time from ale to valid instruction input - 55 ns tllpl time from ale to control pulse psen 17 - ns tplph control pulse duration psen 70 - ns tpliv time from psen to valid instruction input - 12 ns tpxix input instruction hold time after psen 0 - ns tpxiz input instruction float delay after psen - 20 ns taviv address to valid instruction input - 95 ns tplaz to psen address float time - 10 ns external data memory tlhll ale pulse duration 20 - ns tavll address set-up time to ale 17 - ns tllax address hold time after ale 10 - ns trlrh rd pulse duration 80 - ns twlwh wr pulse duration 80 - ns trldv rd to valid data input - 60 ns trhdx data hold time after rd 0 - ns trhdz data float delay after rd 32 - ns tlldv time from ale to valid data input - 90 ns tavdv address to valid input - 105 ns tllwl time from ale to rd or wr 40 140 ns tavwl time from address to rd or wr 45 - ns twhlh time from rd or wr high to ale high 10 55 ns tqvwx data valid to wr transition 10 - ns tqvwh data set-up time before wr 125 - ns twhqx data hold time after wr 10 - ns trlaz address float delay after rd - 0 ns note: 1. the maximun operating frequency is limited to 40 mhz and the minimum to 3.5 mhz.
10 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x external clock drive xtal symbol parameter variable clock unit min max fclk clock frequency 1.2 16 (tbf.) mhz tclcl clock period 63 833 ns tchcx high time 20 tck-tclcx ns tclcx low time 20 tck-tchcx ns tclch rise time - 20 ns tchcl fall time - 20 ns tcy cycle time (tcy = 12 tck) 0.75 10 ms serial port characteristics serial port timing : shift register mode vdd = 5v 10%; vss = 0v; tamb=0 c; load capacitance = 80 pf symbol parameter 33 mhz oscillator unit min max txlxl serial port clock cycle time 360 - ns tqvxh output data setup to clock rising edge 167 - ns txhqx output data hold after clock rising edge 5 - ns txhdx input data hold after clock rising edge 0 - ns txhdv clock rising edge to input data valid - 167 ns external clock drive waveform ac testing input, output waveforms float waveform 0.45v 0.2 vcc-0.1 tchcl tclcx tclcl tclch tchcx vcc-0.5 0.7 vcc 0.2 vcc+0.9 ac inputs during testing are driven at vcc-0.5v for a logic "1" 0.45v for a logic "0". timing measurements are made at vih min for a logic "1" and vil max for a logic "0". 0.2 vcc-0.1 0.45v vcc-0.5 vload timing reference points vload-0.1v vload+0.1v vol+0.1v voh-0.1v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100mv change form the loaded voh/vol level occurs. iol/ioh = + 20 ma
11 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x external program memory read cycle tlhll a8 - a15 a8 - a15 a0 - a7 a0 - a7 instr in ale psen port 0 port 2 tlhiv tpliv tpxiz tplaz tpxix tllax taviv tplip tllpl tavll external data memory read cycle data i n a0-a7 from pcl a8-a15 from pch p2.0-p2.7 or a8-a15 from dph a0-a7 from ri or dpl instr. in ale psen port 0 port 2 tlhll tavll tllax trliz tavwl trlrh twhlh trhdz tllwl tlldl tavdv trhdx trldv rd
12 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x external data memory write cycle data out a0-a7 from pcl a8-a15 from pch p2.0-p2.7 or a8-a15 from dph a0-a7 from ri or dpl instr. in ale psen port 0 port 2 tlhll tavll tllax tavwl twlwh twhlh tllwl tqvwx twhqx tqvwh wr shift register mode timing waveforms ale clock output data write to sbuf input data clear ri instruction 0 0 valid valid valid valid valid valid valid valid 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 txlxl txhqx txhdx tqvxh txhdv
13 p/n:pm0803 rev. 0.0, apr. 23, 2001 mx10l8050x revision history revision description page date 0.0 apr/23/2001
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